The present invention relates to a semiconductor integrated circuit, a method of designing the same, a program recording medium on which a program for supporting designing of the semiconductor integrated circuit is recorded, and a design data recording medium on which design data used for designing the semiconductor integrated circuit is recorded. More particularly, the invention relates to a technique effective for use in a semiconductor integrated circuit suitable for high-speed and low-power operation.
In recent years, a semiconductor integrated circuit device is requested to have improved operating frequency and lower power consumption. In order to improve the operating frequency, generally, the threshold voltage of an insulated gate field effect transistor (hereinbelow, simply called an MIS (Metal Insulated Semiconductor) transistor or a MOS (Metal Oxide Semiconductor) transistor) used in a semiconductor integrated circuit is decreased. When the threshold voltage is set to too low, however, a MOS transistor cannot be completely turned off due to a subthreshold characteristic of the MOS transistor, a subthreshold leak current increases, and a problem such that power consumption of the semiconductor integrated circuit becomes very high occurs. For solving the problem, Japanese Unexamined Patent Publication No. Hei 11(1999)-195976 (first literature) discloses a method of preparing a plurality of kinds of MOS transistors having different threshold voltages and selectively using the MOS transistors in accordance with the degree of timing allowance of a signal path in a semiconductor integrated circuit.
To address the request for reduction in power consumption, Japanese Unexamined Patent Publication No. Hei 10(1998)-189749 (U.S. Pat. No. 6,097,043) (second literature) discloses a method of preparing a plurality of power supply voltages and selectively using a circuit for supplying a high voltage and a circuit for supplying a low voltage, thereby reducing the power.
The method disclosed in the first literature intends to achieve both improvement in operating speed and reduction in leak current in the standby mode by applying a circuit using a MOS transistor of a low threshold voltage to a path having no timing allowance (critical path) and applying a circuit using a MOS transistor having a high threshold voltage to other paths. In a circuit to which the technique is applied, however, when an attempt is made to reduce the power consumption in active operation by decreasing the power supply voltage, the threshold voltage of a MOS transistor has to be also decreased to maintain the operating speed. It was clarified by the examination of the inventors of the present invention that large reduction in power consumption cannot be expected due to the power consumption increased by the leak current in the standby mode.
According to the method disclosed in the second literature, a plurality of power supply voltages are prepared in a semiconductor integrated circuit. By supplying a high voltage to a circuit as a component of a path having no allowance (critical path) and supplying a low voltage to a circuit as a component of a path having an allowance in accordance with the degree of timing allowance of a signal path, the method intends to achieve improved operating speed and reduction in power in active operation. Regarding a circuit to which the technique is applied, however, the inventors of the present invention have uncovered that since a substrate voltage in a MOS transistor to which a high operating voltage is supplied and that in a MOS transistor to which a low operating voltage is supplied are different from each other, an isolating region is necessary in the substrate, and the chip area may increase. Since all of MOS transistors have the same threshold voltage, there is the possibility that power consumption increases due to a leak current in the standby mode.
An object of the invention is to provide a semiconductor integrated circuit realizing high-speed and lower-power operation from the viewpoint of operating power source voltage and substrate bias voltage.
Another object of the invention is to provide a semiconductor integrated circuit without an overhead area, realizing improved operating speed, reduced power consumption in an active mode, and reduced power consumption in a standby mode.
Another object of the invention is to provide a designing method suitable for designing a semiconductor integrated circuit without an overhead area, realizing improved operating speed, reduced power consumption in an active mode, and reduced power consumption in a standby mode. Further another object of the invention is to provide a program recording medium on which a design supporting program suitable for increasing efficiency in designing such a semiconductor integrated circuit is recorded and, further, a design data recording medium on which design data suitable for increasing efficiency in designing such a semiconductor integrated circuit is recorded.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the accompanying drawings.
An embodiment of the invention disclosed in the application will be briefly described as follows.
1.  less than Sharing of Substrate Potential greater than 
From the viewpoint of sharing a substrate potential by logic gates of different operation power sources, a semiconductor integrated circuit has: a first logic gate (1) using, as an operation power source, a first pair of potentials (VDDL and VSSL or VDDL and VSS) having a relatively small potential difference; and a second logic gate (2) using, as an operation power source, a second pair of potentials (VDDH and VSSH or VDDH and VSS) having a relatively large potential difference. Each of the first and second logic gates has an MIS transistor, and substrate potentials (VBP and VBN, or VDDH and VSSH) of the MIS transistors are commonly used by the first and second logic gates.
Since the second logic gate has a larger potential difference of the operation power source as compared with the first logic gate, an output voltage amplitude by the MIS transistors (MP0 and MN0) of the second logic gate is larger than that of the MIS transistors (MP1 and MN1) of the first logic gate. The second logic gate has a relatively higher driving capability and operates at high speed. Since the power consumption in logic operation is proportional to the square of the output voltage amplitude, the first logic gate 1 can operate with less power. At this time, the MIS transistor has a characteristic such that the threshold voltage increases due to a reverse substrate bias applied across the source and the substrate, and the threshold voltage decreases by a forward substrate bias. Since the substrate potentials of the MIS transistors are commonly used by the first and second logic gates, even in the case of generating different substrate bias states in the first and second logic gates, MOS transistors as components of the logic gates can be formed in the common well region. When the substrate potential of the first logic gate and that of the second logic gate are made different from each other, even the conduction type of the MIS transistors is the same, the well regions have to be electrically isolated from each other, and the chip occupying area enlarges due to the isolation areas. The substrate bias states in the first and second logic gates can be set according to the level of the substrate potential and that of the power source potentials of both of the logic circuits. When the forward substrate bias is applied to an MIS transistor included in the second logic gate intended for high speed operation, the threshold voltage decreases, and the operation can be performed at higher speed. On the other hand, when the reverse substrate bias is applied to an MIS transistor included in the first logic gate intended for low power operation, the threshold voltage increases, the subthreshold leak current at the time of non-conduction decreases, and the low power operation is promoted.
As a first example of the substrate bias states which can be set for the first and second logic gates, when the level (VBP) between the high potential side potentials (VDDH and VDDL) at each of the first and second potential pairs and the level (VBN) between the low potential side potentials (VSSL and VSSH) are used as the substrate potentials, the reverse substrate bias can be applied to the MIS transistor in the first logic gate, and the forward substrate bias can be applied to the MIS transistor in the second logic gate. Thus, the second logic gate intended for high speed operation can operate at higher speed, and the first logic gate intended for low power operation can operate with lower power due to reduction in the subthreshold leak current.
As shown in FIG. 1, by using the substrate bias states for both the p-channel type MIS transistor and the n-channel type MIS transistor included in the first and second logic gates, the maximum effect can be produced.
The subthreshold leak is proportional to the gate width of the MIS transistor. Consequently, in consideration of the fact that the gate width of a p-channel type MIS transistor which is generally inferior from the viewpoint of driving capability or electron conductivity tends to be set wider than that of an n-channel type MIS transistor, as shown in FIG. 27, the low power can be realized even when a reverse substrate bias state is generated only for the p-channel type MIS transistor in the first logic gate intended for low power operation.
When the promotion of the low power operation in the first logic gate is mainly considered, as shown in FIG. 25, it is also possible to apply a reverse substrate bias only to the MIS transistor in the first logic gate, and not to apply the substrate bias to the second logic gate.
2.  less than Sharing of Well Region greater than 
The viewpoint of sharing the substrate potential may be also grasped from the viewpoint of sharing the well region in the MIS transistor. A semiconductor integrated circuit has: a first logic gate (1) using, as an operation power source, a first pair of potentials (VDDL and VSSL, VDDL and VSS) having a relatively small potential difference; and a second logic gate (2) using, as an operation power source, a second pair of potentials (VDDH and VSSH, VDDH and VSS) having a relatively large potential difference. Each of the first and second logic gates has an MIS transistor, and well regions (NWELL, PWELL) of the MIS transistor in which the first logic is formed and well region (NWELL, PWELL) in which an MIS transistor of the second logic gate is formed are made common every conduction type. According to the potential applied to the well region in the MIS transistor, the bias state of the MIS transistor is determined. The action at this time is the same as the above 1.
3.  less than Viewpoint of Potential Pair greater than 
In a further detailed mode of the invention by sharing the substrate potentials, a semiconductor integrated circuit includes: a first logic gate (1) using, as an operation power source, a first pair of a high potential and a low potential (VDDL and VSSL, VDDL and VSS); and a second logic gate (2) using, as an operation power source, a second pair of a high potential and a low potential (VDDH and VSSH, VDDH and VSS) having a potential difference larger than that of the first potential pair. Substrate potentials (VBP and VBN, VDDH and VSSH) of MIS transistors in the first logic gate and those of MIS transistors in the second logic gate are common to each other, and at least the first logic gate includes an MIS transistor to which a substrate bias is applied in a reverse direction by the substrate potential.
Specific modes of the pair of the first and second potentials and the substrate potential are as follows. As a first mode, as shown in FIG. 1, the first potential pair includes a first high potential (VDDL) and a first low potential (VSSL), the second potential pair includes a second high potential (VDDH) higher than the first high potential and a second low potential (VSSH) lower than the first low potential, and the substrate potentials includes a high potential side substrate potential (VBP) between the first and second high potentials and a low potential side substrate potential (VBN) between the first and second low potentials. In the mode, as described above, the reverse substrate bias state is achieved in both of the p-channel type MIS transistor and the n-channel type MIS transistor included in the first logic gate, and the forward substrate bias state is achieved in both of the p-channel type MIS transistor and the n-channel type MIS transistor included in the second logic gate.
As a second specific mode, as shown in FIG. 25, the first potential pair includes a first high potential (VDDL) and a first low potential (VSSL), the second potential pair includes a second high potential (VDDH) higher than the first high potential and a second low potential (VSSH) lower than the first low potential, the second high potential (VDDH) is used as a high potential side substrate potential, and the second low potential (VSSH) is used as a low potential side substrate potential. This mode is used when the reverse bias state is achieved in both p-channel type and n-channel type MIS transistors included in the first logic gate, and the substrate bias is not applied to the MIS transistors included in the second logic gate. According to the mode, while promoting the reduction in subthreshold leak in the first logic gate, at least two lines for the power sources and the substrate bias can be reduced as compared with the first mode.
As a third mode, as shown in FIG. 27, the first potential pair includes a first high potential (VDDL) and a first low potential (VSS), the second potential pair includes a second high potential (VDDH) higher than the first high potential and the first low potential (VSS), a potential (VBP) between the first and second high potentials is used as a high potential side substrate potential, and a potential (VBN) higher than the first low potential is used as a low potential side substrate potential. In the mode, the reverse substrate bias state is achieved only for the p-channel type MIS transistor included in the first logic gate, and the forward substrate bias is applied to the n-channel type MIS transistor included in the first logic gate and the n-channel type and p-channel type MIS transistors included in the second logic gate. As described above, by paying attention to the point that the gate width of the p-channel type MIS transistor is wider than that of the n-channel type MIS transistor in consideration of the driving capability or electron conductivity, the reverse substrate bias is applied only to the p-channel type MIS transistor in the first logic gate intended for low power operation. While promoting reduction in the subthreshold leak in the first logic gate, at least one line for the power source and substrate bias can be reduced as compared with the first mode.
4.  less than Viewpoint of Power Source Line greater than 
According to further another detailed mode of commonly using the substrate potentials, a semiconductor integrated circuit includes: a first logic gate (1) connected to a first pair of a high potential line and a low potential line (VDDL and VSSL, VDDL and VSS); and a second logic gate (2) connected to a second pair of a high potential line and a low potential line (VDDH and VSSH, VDDH and VSS) having a potential difference larger than that of the first potential line pair. A line of substrate potentials (VBP and VBN, VDDH and VSSH) for supplying a substrate potential to an MIS transistor of the first logic gate and a substrate potential line for supplying a substrate potential to an MIS transistor of the second logic gate are commonly used, and at least the first logic gate includes an MIS transistor to which a substrate bias is applied in a reverse direction by the substrate potential.
The specific modes of the first and second potential lines and the substrate potential line correspond to the first to third modes in 3. In the first mode, the first potential line pair includes a first high potential line (VDDL) and a first low potential line (VSSL), the second potential line pair includes a second high potential line (VDDH) having a potential higher than that of the first high potential line and a second low potential line (VSSH) having a potential lower than the first low potential line, and the substrate potential lines include a high potential side substrate potential line (VBP) having a potential between the potential of the first high potential line and the potential of the second high potential line, and a low potential side substrate potential line (VBN) having a potential between the potential of the first low potential line and the potential of the second low potential line.
In the second mode, the first potential line pair includes a first high potential line (VDDL) and a first low potential line (VSSL), the second potential line pair includes a second high potential line (VDDH) having a potential higher than that of the first high potential line and a second low potential line (VSSH) having a potential lower than that of the first low potential line, and the second high potential line (VDDH) is used as a high potential side substrate potential line, and the second low potential line (VSSH) is used as a low potential side substrate potential line.
In the third mode, the first potential line pair includes a first high potential line (VDDL) and a first low potential line (VSS), the second potential line pair is a second high potential line (VDDH) having a potential higher than that of the first high potential line and is the first low potential line (VSS), and the substrate potential line is a high potential side substrate potential line having a potential (VBP) between the potential of the first high potential line and the potential of the second high potential line, and is a low potential side substrate potential line having a potential (VBN) higher than the potential of the first low potential line.
5.  less than Viewpoint of Layout greater than 
The viewpoint of sharing the substrate potentials may be grasped from the viewpoint of layout of a semiconductor integrated circuit. A semiconductor integrated circuit has a circuit region in which a number of logic gates each having an MIS transistor are arranged on a semiconductor substrate. The circuit region has well regions (NWELL, PWELL) shared by a substrate potential every conduction type of an MIS transistor. In the well regions, a first logic gate (1) using, as an operation power source, a first pair of potentials (VDDL and VSSL, VDDL and VSS) having a relatively small potential difference and a second logic gate (2) using, as an operation power source, a second pair of potentials (VDDH and VSSH, VDDH and VSS) having a relatively large potential difference are formed. In the well regions, a p-type well region (PWELL) in which an n-channel type MIS transistor is formed and an n-type well region (NWELL) in which a p-channel type MIS transistor is formed are adjacent to each other, and metal lines for supplying the first pair of potentials, the second pair of potentials, and a substrate potential are arranged on the well region.
By the configuration as well, the actions similar to the above 1 can be obtained. A semiconductor integrated circuit without an overhead area, realizing improved operating speed, reduced power consumption in an active mode, and reduced power consumption in a standby mode can be realized.
6.  less than Viewpoint of Signal Amplitude greater than 
The potential difference of the operation power source can be grasped from the viewpoint of an output signal amplitude. From this viewpoint, a semiconductor integrated circuit includes: a first logic gate (1) for generating a relatively small output signal amplitude by using a first pair of potentials (VDDL and VSSL, VDDL and VSS) as an operation power source; and a second logic gate (2) for generating a relatively large output signal amplitude by using a second pair of potentials (VDDH and VSSH, VDDH and VSS) as an operation power source. Substrate potentials (VBP and VBN, VDDH and VSSH) of MIS transistors in the first logic gate and those of MIS transistors in the second logic gate are common to each other. The actions of the configuration are also the same as those of 1.
As a further specific mode, attention is paid to a clock synchronous signal path including the first and second logic gates. Specifically, the first logic gate includes a sequence circuit and a combinational circuit, the second logic gate includes a sequence circuit and a combinational circuit, a plurality of unit signal paths each leading from a sequence circuit to a sequence circuit at the next stage via one or a plurality of combinational circuits are provided, and the plurality of unit signal paths includes a unit signal path in which the first and second logic gates mixedly exist.
In a unit signal path in which the first and second logic gates exist mixedly, the second logic gate is disposed on the upstream side of the first logic gate. By the configuration, a signal having a small signal amplitude is supplied to a circuit having a large output signal amplitude, and an output becomes at the intermediate level. Thus, a situation that a through current occurs can be easily checked.
In order to increase the degree of freedom against the limitation, it is sufficient to use the sequence circuit (F81) adopting the clock synchronous level shifting function. Specifically, in a unit signal path in which the first and second logic gates exist mixedly, a sequence circuit including the second logic gate for receiving an output of a combinational circuit including the first logic gate has, at its input stage, a clock synchronous type level shifting circuit (20) for shifting the level of an input signal amplitude to the level of an output signal amplitude of the second logic gate synchronously with a clock signal. By performing a level shifting operation synchronously with the operation of the sequence circuit for latching an input signal synchronously with the clock signal, the signal propagation delay caused by the level shifting operation can be easily suppressed.
The level shifting function is not limited to be synchronized with a clock. In a unit signal path in which the first and second logic gates exist mixedly, the second logic gate for receiving an output of the first logic gate is a level shifting circuit (G94) for shifting the level of an output signal amplitude of the first logic gate to the level of an output signal amplitude of the second logic gate, and a second logic gate circuit may be connected to an output of the level shifting circuit in series.
7.  less than Designing Method greater than 
A method of designing a semiconductor integrated circuit by using a first logic gate and a second logic gate in which substrate potentials of MIS transistors of the same conduction type are equal to each other, includes: a first step of determining whether a signal propagation delay time of a signal path in a logic circuit designed by using the first logic gate using, as an operation power source, a first pair of potentials (VDDL and VSSL, VDDL and VSS) having a relatively small potential difference achieves a target time or not; and a second step of replacing one or a plurality of first logic gates included in a signal path having a signal propagation delay time which does not achieve the target time in the first step with a second logic gate using, as an operation power source, a second pair of potentials (VDDH and VSSH, VDDH and VSS) having a relatively large potential difference. By the designing method, timing allowance necessary for a critical path can be easily allowed to be assured. As a result, the designing of the semiconductor integrated circuit without an overhead area, realizing improved operation speed, reduced power consumption in an active mode, and reduced power consumption in a standby mode is facilitated.
When the required timing allowance cannot be obtained by one replacement operation, it is sufficient to include a third step for determining whether a signal propagation delay time of the signal path in which replacement is performed in the second step achieves the target time or not and, if it does not achieve the target time, replacing another first logic gate included in the signal path with a second logic gate.
As a means for suppressing a situation that a signal having a small amplitude is supplied to a circuit having a large output signal amplitude, an output becomes at an intermediate level, and a through current occurs, in the second and third steps, the replacement with the second logic gate is performed from the upstream side of the signal path. Consequently, although the degree of freedom in the replacing position is low to a certain extent, the through current can be easily checked by the replacement rule.
In order to increase the degree of freedom in designing against the limitation, it is sufficient to use the sequence circuit (F81) adopting the clock synchronous level shifting function. In the second and third steps, when the second logic gate as a sequence circuit is disposed at the next stage of a first logic gate, the second logic gate has, at its input stage, a clock synchronous type level shifting function for shifting the level of an input signal amplitude to the level of an output signal amplitude of the second logic gate synchronously with the clock signal.
In order to increase the degree of freedom in designing against the limitation of using the sequence circuit with the clock synchronous level shifting function, in the second and third steps, when the second logic gate is disposed at the next stage of the first logic gate, it is sufficient to use the method of inserting a level shifting circuit (G94) for shifting the level of an output signal amplitude to the level of an output signal amplitude of the second logic gate in front of the second logic gate.
8.  less than Program Recording Medium greater than 
On a program recording medium (91), a program for supporting designing of a semiconductor integrated circuit using a first logic gate and a second logic gate in which a substrate potential of MIS transistors of the same conduction type are equal to each other is recorded so as to be read by a computer (90). The program executes: a first step of determining whether a signal propagation delay time of a signal path in a logic circuit designed by using the first logic gate using, as an operation power source, a first pair of potentials (VDDL and VSSL, VDDL and VSS) having a relatively small potential difference achieves a target time or not; and a second step of replacing one or a plurality of first logic gates included in a signal path having a signal propagation delay time which does not achieve the target time in the first step with a second logic gate using, as an operation power source, a second pair of potentials (VDDH and VSSH, VDDH and VSS) having a relatively large potential difference. By reading the program from the recording medium and executing it by the computer, the designing of a logic circuit by the designing method is facilitated.
When the case where predetermined timing allowance cannot be obtained by one replacing operation is considered in advance, the program can further execute a third step for determining whether a signal propagation delay time of the signal path in which replacement is performed in the second step achieves the target time or not and, if it does not achieve the target time, replacing another first logic gate included in the signal path with a second logic gate.
9.  less than Design Data Recording Medium greater than 
On a design data recording medium (91), design data for designing an integrated circuit to be formed on a semiconductor chip by using a computer is recorded so as to be read by the computer. The design data includes: first mask pattern data for determining a figure pattern for forming a first logic gate to which an operation power source is supplied from a first pair of potential lines (VDDL and VSSL, VDDL and VSS) having a relatively small potential difference and a substrate potential is supplied from a substrate potential line on the semiconductor chip; and second mask pattern data for determining a figure pattern for forming a second logic gate to which an operation power source is supplied from a second pair of potential lines (VDDH and VSSH, VDDH and VSS) having a relatively large potential difference and a substrate potential is supplied from a substrate potential line on the semiconductor chip. The design data recorded on the design data recording medium is, for example, verified mask pattern data for forming what is called a hardware IP module. By using the data for designing a layout by a computer, the designing of the semiconductor integrated circuit from the viewpoint of sharing the substrate potentials can be extremely facilitated.
The design data may be data described in a hardware description language such as what is called a software IP module. Specifically, design data recorded on a design data recording medium (91) so as to be read by a computer includes: first function description data for determining a function of a first logic gate to which an operation power source is supplied from a first pair of potential lines (VDDL and VSSL, VDDL and VSS) having a relatively small potential difference and a substrate potential is supplied from a substrate potential line; and second function description data for determining a function of a second logic gate to which an operation power source is supplied from a second pair of potential lines (VDDH and VSSH, VDDH and VSS) having a relatively large potential difference and a substrate potential is supplied from a substrate potential line connected to the substrate potential line. The function description data does not specify a circuit pattern unlike mask pattern data. Instead, the degree of freedom in a layout pattern is relatively high and a function change is relatively easily made.